`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:05:36 05/09/2012
// Design Name:   VerilogDebug
// Module Name:   C:/achdmips/trunk/hdl/L2Cache/DebugTEST.v
// Project Name:  L2Cache
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VerilogDebug
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module DebugTEST;

	// Inputs
	reg clk;
	reg a_in;
	reg b_in;

	// Outputs
	wire c_out;

	// Instantiate the Unit Under Test (UUT)
	VerilogDebug uut (
		.clk(clk), 
		.a_in(a_in), 
		.b_in(b_in), 
		.c_out(c_out)
	);

	reg ready = 0;
	initial begin
		// Initialize Inputs
		clk = 0;
		a_in = 0;
		b_in = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		ready = 1;
	end
	
	always begin
		clk <= 0;
		#5;
		clk <= ready;
		#5;
		
		if( ready )
			$display("---CLOCK---");
	end
	
	reg[15:0] testcount = 0;
	always @(posedge clk) begin
		
		case(testcount)
			0: begin
				testcount <= 1;
				a_in <= 1;
				b_in <= 0;
			end
			
			1: begin
				testcount <= 2;
				a_in <= 1;
				b_in <= 1;
			end
			
			2: begin
			end
		endcase
	end
      
endmodule

